For progress in microelectronics, it is important to have tools for inspecting microelectronical structures on a chip or wafer with ever increasing spatial resolution. At the same time, it is important to decrease the costs of such inspections in order for the industry to fabricate devices of ever increasing complexity at low costs.
A prominent tool for such inspections is the scanning electron microscope (SEM). The SEM uses a primary electron beam as a means to probe the surface structure of a given specimen. An interaction of the primary electron beam with the specimen causes electrons to be released into a backward direction with respect to the primary electron beam where they are detected by an electron detector. By scanning the primary electron beam across the specimen and determining the rate of the released electrons at each scan position, an image of the surface of the specimen with high spatial resolution is obtained. The spatial resolution of the image is essentially given by the size of the beam focus.
Due to the progressing miniaturization of integrated circuits, it has become important to study the crystal and layer structure of an integrated circuit structure below the surface of the wafer. This is usually done by inspecting a cross sectional thin slice (membrane) from the wafer or chip by means of a transmission electron microscope (TEM). With a TEM, a spatial resolution down to the atomic scale can be achieved, which is sufficient to analyze crystal structures and layers which may be only a few atomic layers thick. The TEM is characterized in that it detects electrons which have been transmitted through the specimen. Therefore, the detector of a TEM is positioned behind the specimen. Further, instead of using a scanning unit for generating an image, a TEM comprises a complex electron beam optics between the detector and the specimen to project and magnify an image of the specimen structure onto the detector. In order to capture the image of the specimen structure with high precision, the TEM detector needs to be highly segmented e.g. like a CCD.
The preparation and manipulation of a membrane of a wafer or chip for a TEM inspection represents a major complication because the use of a TEM requires that the membrane is sufficiently thin (typically 10 to 100 nm thickness) in order for the primary electrons to be transmitted through the sample. Fabrication and handling of such thin membranes is no easy task. In recent years, however, the use of focussed ion beam devices (FIB) for etching a membrane from a wafer has been established which significantly simplifies the sample preparation, see e.g. U.S. Pat. No. 6,188,068 by F. Shaapur and R. Graham, or B. Köhler and L. Bischoff “Entwicklung einer neuen Technologie zur Probenpräparation für die Transmissions-Elektronenmikroskopie (TEM) auf der Basis der Ionenfeinstrahlbearbeitung” from “Wissenschaftlich-Technische Berichte”, FZR-329, August 2001, ISSN 1437-322X, Forschungszentrum Rossendorf.
Despite the progress in TEM sample preparation and TEM inspection, it is still complicated, expensive and time-consuming to carry out a TEM inspection because of the many steps needed for each measurement. For example, for a TEM integrated circuit failure analysis, it is required to (a) determine the position of the defect on the wafer or chip surface; this step is usually performed by an SEM inspection; (b) preparing a cross sectional membrane from the wafer at the defective position; this step is usually performed by a FIB; the FIB may be combined with a second SEM in order to observe and control the etching of the wafer; (c) moving the membrane into the TEM, and (d) inspecting the membrane by means of the TEM.
Each of the steps is time-consuming and has its own pitfalls. E.g., step (b) is highly critical because of the mechanical fragility of the very thin membrane; step (c) is critical because of a possible pollution of the membrane in the atmospheric environment during transport; and step (d) is expensive because the TEM itself is an expensive device, is difficult to operate which requires experts that can operate the TEM and evaluate the measurements. Further, to carry out the steps (a) through (d) for a TEM membrane inspection requires an SEM, a FIB or FIB/SEM system, and a TEM, which together are expensive. Further, SEM, FIB and TEM each require a high quality vacuum for operation. Providing such a vacuum each time when a wafer is taken in and out of the respective device is time-consuming.
For these reasons, inspections of cross sectional thin slices of a specimen, in particular the inspection of membranes of a wafer or chip, are expensive. Cross sectional inspections for a failure analysis of integrated circuits on a regular basis are therefore not possible.
It is therefore a first aspect of the present invention to provide an apparatus and method for inspecting a sample of a specimen which does not have the above mentioned disadvantages.
It is a further aspect of the present invention to provide an apparatus for inspecting a cross sectional slice (membrane) of a wafer in a cost- and time-saving way, to make it available in high-throughput production lines.
It is a further aspect of the present invention to provide an apparatus for inspecting a membrane which reduces wafer handling problems and exposure of the membrane to an atmospheric environment.
It is a further aspect of the present invention to provide an apparatus for inspecting a membrane of a wafer which can be integrated into existing semiconductor fabrication lines in an efficient way.